`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/24/2019 12:58:39 PM
// Design Name: 
// Module Name: clock_cyx_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clock_cyx_tb(

    );
    
    reg clk100m_tb, clk100m_ext_tb;
    wire[3:0] d3, d2, d1, d0;
    
    wire[3:0] EN_tb;
    wire[7:0] digi_tb;
    wire buzzer_tb, CO_tb;
    reg clr;
    wire clr_tb;
    wire clk100m_tb_w, clk100m_ext_tb_w;
    
    assign clk100m_tb_w = clk100m_tb;
    assign clk100m_ext_tb_w = clk100m_ext_tb;
    assign clr_tb = clr;
    
    initial
    begin
        clr = 1;
        #100 clr = 0;
        clk100m_tb = 0;
        forever
        begin
            #100 clk100m_tb = ~clk100m_tb;
        end
    end
    
    
    clock_cyx
        #(.clock_freq(10000000))
    clock_tb(
        .clk100m(clk100m_tb_w),
        //.clk_ext(clk100m_ext_tb_w),
        .clear(clr_tb),
        .buzz_state(0),
        .EN(EN_tb),
        .digi(digi_tb),
        .buzzer(buzzer_tb),
        .CO_hrs(CO_tb)//,
        //.digi3(d3),
        //.digi2(d2),
        //.digi1(d1),
        //.digi0(d0)
    );
endmodule
